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1/19 features 4.5v to 14v wide input supply voltage range built-in mosfet and synchronous rectifier 0.8v, high accuracy reference (1%) current-mode control with simple compensation circuit external synchronization power good protection thermal shutdown overvoltage transient protection overcurrent protection 32-pin 4mm x 4mm tqfn package applications fpga and dsp supplies video processor supplies applications processor power description the xr77103-a0r5 universal pmic features three 2a synchronous high-efficiency, buck regulators with integrated power switches. they can operate in 5v, 9v and 12v powered systems with minimal required external component thus providing the smallest size solution possible. two of the outputs may be paralleled for output currents up to 5a peak with steady state current of up to 4a. the output voltage of each converter can be adjusted by external resistor divider down to voltage as low as 0.8v. with a nominal switching frequency of 500khz, the regulators can also be synchronized to an external clock in applications where emi control is critical. xr77103-a0r5 features a supervisor circuit that monitors each converter output. pgood pin is asserted once sequencing is done, outputs are reported in regulation and the reset timer expires. the polarity of the signal is active high. a pulse skipping mode (psm) reduces switching losses maintaining high efficiency when the system is unloaded or in standby mode. universal pmic 3-output buck regulator xr 77103 -a 0 r 5 rev1a
2/19 typical application figure 1. typical application xr77103-a0r5 v in = 5.5 to 14v 25 26 osc pgood internal supply 31 15 10 6 24 27 19 5 ep vin3 vin2 vin1 vcc pgood gnd dgnd agnd en sync start-up bgr 28 4 vin vin pgood buck2 17 18 v out2 = 0.8 to 6v comp2 vfb2 lx2 bst2 lx2 16 14 13 buck1 8 7 v out1 = 0.8 to 6v comp1 vfb1 lx1 bst1 lx1 9 12 11 buck3 1 2 v out3 = 0.8 to 6v comp3 vfb3 lx3 bst3 lx3 32 30 29 xr 77103 -a 0 r 5 rev1a
3/19 absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. v in1 , v in2 , v in3 , lx1, lx2, lx3 ....................... -0.3v to 18v en, v cc ............................................................. -0.3v to 7v pgood, sync ................................................. -0.3v to 7v bst# to lx# ...................................................... -0.3v to 7v agnd, dgnd to gnd .................................... -0.3v to 0.3v storage temperature .................................... -65c to 150c junction temperature ................................................. 150c power dissipation ..................................... internally limited lead temperature (soldering, 10 seconds) ................ 260c cdm ............................................................................ 700v esd rating (hbm C human body model) ....................... 2kv operating conditions v in ..................................................................... 4.5v to 14v v cc ................................................................... 4.5v to 5.5v lx# ................................................................ -0.3v to 14v (1) junction temperature range (t j ) .................. -40c to 125c xr77103 package power dissipation max at 25c ..... 3.4w xr77103 thermal resistance ja ............................. 30c/w note: 1. lx# pins dc range is from -0.3v, transient -1v for less than 10ns. electrical characteristics t a = 25c, v in = 12v, en = v cc , f sw = 500khz, unless otherwise specified. limits applying over the full operating temperature range are denoted by a ?. symbol parameter conditions ? min typ max units power supply characteristics v in input voltage range ? 5.5 14 v v in input voltage range v cc tied to v in ? 4.5 5.5 v v uvlo uvlo threshold v in rising/falling 4.22/4.1 v uvlo deglitch uvlo deglitch rising/falling 220 s i vin v in supply current en = gnd 250 a i vinq en = high, no load 2.6 ma internal supply voltage v cc internal biasing supply i load = 0ma ? 4.9 5 5.1 v i cc internal biasing supply current v in = 12v ? 10 ma v uvlo uvlo threshold for v cc v cc rising 3.8 v v cc falling 3.6 v uvlo deglitch uvlo deglitch for v cc falling edge 220 s xr 77103 -a 0 r 5 rev1a
4/19 electrical characteristics (continued) t a = 25c, v in = 12v, en = v cc , f sw = 500khz, unless otherwise specified. limits applying over the full operating temperature range are denoted by a ?. symbol parameter conditions ? min typ max units protections t sd thermal shutdown temperature temperature rising, non-latch off. t sd release threshold, temperature = t sd -hy tsd 160 c hy tsd thermal shutdown hysteresis 20 c t sd_deglitch thermal shutdown deglitch 220 s v ovbuck threshold voltage for buck over voltage output rising (hs fet will be forced off) 109 % output falling (hs fet will be allowed to switch) 107 % buck converter f sw switching frequency 500 khz t ss soft-start period 6 ms i limx peak inductor current limit 3.5 a r on_hsx hs switch on-resistance v in = 12v 200 m r on_ls1 ls switch on-resistance of buck1 v in = 12v 60 m r on_ls2/3 ls switch on-resistance of buck2/3 v in = 12v 80 m i ox output current capability continuous loading (1) 2 a d max maximum duty cycle 95 % t on min minimum on time 120 ns line regulation (v ox /v inx ) v inx = 5.5 to 14v, i ox = 1a 0.5 %v o load regulation (v ox /i ox ) i o = 10 to 90%, i o = max 0.5 %v o /a output voltage accuracy v in = 12v ? -1 normal 1 % 5.5v v in 14v ? -2 normal 2 sync freq synchronization frequency 525 khz sync d_min synchronization signal minimum duty cycle ? 40 % sync d_max synchronization signal maximum duty cycle ? 60 % note: 1. subject to thermal derating. design must not exceed the package thermal rating. xr 77103 -a 0 r 5 rev1a
5/19 electrical characteristics (continued) t a = 25c, v in = 12v, en = v cc , f sw = 500khz, unless otherwise specified. limits applying over the full operating temperature range are denoted by a ?. symbol parameter conditions ? min typ max units power good reset generator v uvbuck threshold voltage for buck under voltage output falling, (disabled after t on_hiccup ) 85 % output rising, (pg will be asserted) 90 t pg_deglitch deglitch time rising and falling 22 ms t on_hiccup hiccup mode on time v uvbuckx asserted 24 ms t off_hiccup hiccup mode off time once t off_hiccup elapses, all converters will start up again 30 ms t rp minimum reset period 2 s r pg power good pull-down on resistance 14 50 input threshold (sync, en) v ih input threshold high v input rising ? 2.07 2.53 v v il input threshold low v input falling ? 1.36 1.67 v xr 77103 -a 0 r 5 rev1a
6/19 pin configuration pin functions pin number pin name description 1 vfb3 buck 3 feedback pin. 2 comp3 compensation pin for buck 3. connect a series rc circuit to this pin for compensation. 3 nc no connect. 4 vin ic supply pin. connect a capacitor as close as possible to this pin. 5 gnd ground. 6 vcc internal supply. connect a ceramic capacitor from this pin to ground. 7 comp1 compensation pin for buck 1. connect a series rc circuit to this pin for compensation. 8 vfb1 buck 1 feedback pin. 9 bst1 bootstrap capacitor for buck 1. connect a bootstrap capacitor from this pin to lx1. 10 vin1 input supply for buck 1. connect a capacitor as close as possible to this pin. 11 lx1 switching node for buck 1. 12 lx1 switching node for buck 1. 13 lx2 switching node for buck 2. 14 lx2 switching node for buck 2. 15 vin2 input supply for buck 2. connect a capacitor as close as possible to this pin. 16 bst2 bootstrap capacitor for buck 2. connect a bootstrap capacitor from this pin to lx2. 17 vfb2 buck 2 feedback pin. 18 comp2 compensation pin for buck 2. connect a series rc circuit to this pin for compensation. 19 dgnd digital ground. 20 nc no connect. bst1 comp3 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 vfb3 nc pgood sync gnd vfb1 comp1 vin1 lx1 vin2 bst2 nc dgnd nc nc nc en vfb2 comp2 bst3 vin3 lx3 vin agnd vin lx3 lx1 lx2 lx2 vcc xr 77103 -a 0 r 5 rev1a
7/19 pin functions (continued) pin number pin name description 21 nc no connect. 22 nc no connect. 23 nc no connect. 24 pgood power good output. open drain output asserted after all converters are sequenced and within regulation. 25 sync external clock input pin. connect to signal ground when unused. 26 en enable control input. set en high to enable converters. 27 agnd analog ground. 28 vin ic supply pin. connect a capacitor as close as possible to this pin. 29 lx3 switching node for buck 3. 30 lx3 switching node for buck 3. 31 vin3 input supply for buck 3. connect a capacitor as close as possible to this pin. 32 bst3 bootstrap capacitor for buck 3. connect a bootstrap capacitor from this pin to lx3. - e-pad connect to power ground. xr 77103 -a 0 r 5 rev1a
8/19 typical performance characteristics all data taken at f sw = 500khz, t a = 25c, no airflow, unless otherwise specified. - 2 - 1.5 - 1 - 0.5 0 0.5 1 1.5 2 0 0.4 0.8 1.2 1.6 2 i out (a) ?v out /v out (%) - 2 - 1.5 - 1 - 0.5 0 0.5 1 1.5 2 0 0.4 0.8 1.2 1.6 2 i out (a) ?v out /v out (%) figure 4. load regulation channel 2, 12v in , 1.8v out figure 5. load regulation channel 2, 5v in , 1.8v out - 2 - 1.5 - 1 - 0.5 0 0.5 1 1.5 2 0 0.4 0.8 1.2 1.6 2 i out (a) ?v out /v out (%) - 2 - 1.5 - 1 - 0.5 0 0.5 1 1.5 2 0 0.4 0.8 1.2 1.6 2 i out (a) ?v out /v out (%) figure 2. load regulation channel 1, 12v in , 3.3v out figure 3. load regulation channel 1, 5v in , 3.3v out - 2 - 1.5 - 1 - 0.5 0 0.5 1 1.5 2 0 0.4 0.8 1.2 1.6 2 i out (a) ?v out /v out (%) - 2 - 1.5 - 1 - 0.5 0 0.5 1 1.5 2 0 0.4 0.8 1.2 1.6 2 i out (a) ?v out /v out (%) figure 6. load regulation channel 3, 12v in , 1.2v out figure 7. load regulation channel 3, 5v in , 1.2v out xr 77103 -a 0 r 5 rev1a
9/19 typical performance characteristics (continued) all data taken at f sw = 500khz, t a = 25c, no airflow, unless otherwise specified. v out ac 20mhz i out di/dt 2.5a/s 68.0mv -62.0mv v out ac 20mhz i out di/dt 2.5a/s 148.0mv -132.0mv figure 10. 12v in , 3.3v out transient response, 0.5a to 1.0a figure 11. 12v in , 1.8v out transient response, 0.5a to 1.0a v out ac 20mhz i out di/dt 2.5a/s 180.0mv -172.0mv enable channel 3 channel 2 channel 1 figure 8. power-up sequence figure 9. 12v in , 5.0v out transient response, 0.5a to 1.0a v out ac 20mhz i out di/dt 2.5a/s 68.0mv -66.0mv v out ac 20mhz i out di/dt 2.5a/s 164.0mv -160.0mv figure 12. 5v in , 3.3v out transient response, 0.5a to 1.0a figure 13. 5v in , 1.8v out transient response, 0.5a to 1.0a xr 77103 -a 0 r 5 rev1a
10/19 typical performance characteristics (continued) efficiency f sw = 500khz, t a = 25c, no airflow, only individual channel operating, inductor losses are included. i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 16. efficiency channel 2, 12v in 1.8v out figure 17. efficiency channel 2, 5v in 1.8v out i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 14. efficiency channel 1, 12v in 3.3v out figure 15. efficiency channel 1, 5v in 3.3v out i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 i out (a) ef?ciency (%) 0 10 20 30 40 50 60 70 80 90 10 0 0 0.4 0.8 1.2 1.6 2 figure 18. efficiency channel 3, 12v in 1.2v out figure 19. efficiency channel 3, 5v in 1.2v out xr 77103 -a 0 r 5 rev1a
11/19 typical performance characteristics (continued) thermal characteristics i out (a) power loss (w) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.4 0.8 1.2 1.6 2 1.2v 1.8v 3.3v 0.9 i out (a) power loss (w) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.4 0.8 1.2 1.6 2 1.2v 1.8v 3.3v 0.9 figure 22. channel 2 power loss at f sw = 500khz, v in = 12v, no airflow figure 23. channel 3 power loss at f sw = 500khz, v in = 12v, no airflow i out (a) power loss (w) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.4 0.8 1.2 1.6 2 1.2v 1.8v 3.3v t ambient (c) power dissipation in package (w) 0 0.5 1 1.5 2 2.5 3 3.5 4 0 10 20 30 40 50 60 70 80 90 100 110 120 figure 20. package thermal derating figure 21. channel 1 power loss at f sw = 500khz, v in = 12v, no airflow i out (a) power loss (w) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.4 0.8 1.2 1.6 2 1.2v 1.8v 3.3v i out (a) power loss (w) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.4 0.8 1.2 1.6 2 1.2v 1.8v 3.3v 1.2v 1.8v 3.3v figure 24. channel 1 power loss at f sw = 500khz, v in = 5v, no airflow figure 25. channel 2 power loss at f sw = 500khz, v in = 5v, no airflow xr 77103 -a 0 r 5 rev1a
12/19 typical performance characteristics (continued) thermal characteristics i out (a) power loss (w) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.4 0.8 1.2 1.6 2 1.2v 1.8v 3.3v figure 26. channel 3 power loss at f sw = 500khz, v in = 5v, no airflow xr 77103 -a 0 r 5 rev1a
13/19 functional block diagram xr77103-a0r5 25 26 osc pgood internal supply 31 15 10 6 24 27 19 5 ep vin3 vin2 vin1 vcc pgood gnd dgnd agnd en sync buck1 9 12 11 8 7 buck2 16 14 13 17 18 buck3 32 30 29 1 2 comp3 vfb3 lx3 bst3 start-up bgr 28 4 vin vin lx3 comp1 vfb1 lx1 bst1 lx1 comp2 vfb2 lx2 bst2 lx2 figure 27. functional block diagram xr 77103 -a 0 r 5 rev1a
14/19 applications information operation xr77103-a0r5 is a power management ic with three step-down buck converters. both high-side and low-side mosfets are integrated to provide fully synchronous conversion with higher efficiency. xr77103-a0r5 can support 4.5v to 14v input supply, high load current, 500khz clocking. the buck converters have a psm mode which can improve power dissipation during light loads. alternatively, the device implements a constant frequency mode. the sync pin also provides a means to synchronize the power converter to an external signal. input ripple is reduced by 180 degree out-of-phase operation among converters. all three buck converters have peak current mode control which simplifies external frequency compensation. each buck converter has peak inductor current limit of 3.5a. the device has a power good comparator monitoring the output voltage. soft-start for each converter is 6ms. all outputs start up once en pin is set high. output voltage setting output voltage is set externally using an external resistor divider. output voltage is determined by the following equation. v outx = 0.8v x 1 + r1 r2 r1 r2 v outx xr77103-a0r5 figure 28. output voltage setting this can make the device applicable to avs (automatic voltage scaling) system. output voltage can be adjusted automatically by external dc voltage. figure 29 shows application circuit of supply for avs system. xr77103-a0r5 soc v fbx v outx r1 r dac avs supply pvt mnt v dac r2 figure 29. avs control frequency compensation in order to properly frequency compensate the device, the following component selection is recommended. v in (v) v out (v) l (h) c out (f) r comp (k?) c comp (nf) 12/5.0 1.0 2.2 22 x 3 10 4.7 12/5.0 1.2 2.2 22 x 3 10 4.7 12/5.0 1.5 3.3 22 x 3 20 4.7 12/5.0 1.8 3.3 22 x 2 20 4.7 12/5.0 2.5 4.7 22 x 2 20 4.7 12/5.0 3.3 4.7 22 x 1 20 4.7 12 5.0 6.8 22 x 1 20 4.7 synchronization the status of the sync pin will be ignored during start- up and the xr77103-a0r5s control will only synchronize to an external signal after the pgood signal is asserted. when synchronization is applied, the sync pulse frequency must be higher than the pwm oscillator frequency (525khz) to allow the external signal trumping the oscillator pulse reliably. when synchronization is not applied, the sync pin should be connected to signal ground. although the device can lock to external clock running up to 2.31mhz, doing this will alter the timing characteristics and degrade thermal performance. xr 77103 -a 0 r 5 rev1a
15/19 applications information (continued) out-of-phase operation channels 1 and 2 operate in phase while channel 3 operates 180 degrees out-of-phase with the other two converters (see figure 30). this enables the system, having less input ripple, to lower component cost, save board space and reduce emi. lx1 lx2 lx3 figure 30. out-of-phase operation two buck regulators in parallel operation (current sharing) the xr77103-a0r5 can be used in parallel operation to increase output current capacity. to enable this, a user needs: to connect v out2 and v out3 together. to connect comp2 and comp3 together. regulate the channels 2 and 3 to the same v out . then, the channels 2 and 3 will run in parallel and load current is shared in average. buck2 comp2 vfb2 lx2 lx2 vfb3 lx3 lx3 comp3 v out buck3 figure 31. parallel operation power good the pgood pin is an open drain output. the pgood pin is pulled low when any buck converter is pulled below 85% of the nominal output voltage. the pgood is pulled up when all three buck converters outputs are more than 90% of their nominal output voltage and the pgood reset timer expires. the polarity of the pgood is active high. the pgood reset time is 2s. thermal design proper thermal design is critical in controlling device temperatures and in achieving robust designs. there are a number of factors that affect the thermal performance. one key factor is the temperature rise of the devices in the package, which is a function of the thermal resistances of the devices inside the package and the power being dissipated. the thermal resistance of the xr77103-a0r5 (30c/w) is specified in the operating conditions section of this datasheet. the ja thermal resistance specification is based on the xr77103-a0r5 evaluation board operating without forced airflow. since the actual board design in the final application will be different, the thermal resistances in the final design may be different from those specified. the package thermal derating and power loss curves are shown in figures 20 through 26. these correspond to input voltages of 12v and 5v. layout guidelines proper pcb layout is crucial in order to obtain a good thermal and electrical performance. for thermal considerations it is essential to use a number of thermal vias to connect the central thermal pad to the ground layer(s). in order to achieve good electrical and noise performance following steps are recommended: place the output inductor close to the lx pins and minimize the area of the connection. doing this on the top layer is advisable. central thermal pad shall be connected to the power ground connections to as many layers as possible. output filtering capacitor shall share the same power ground connection as the input filtering capacitor. connection to the signal ground plane shall be done with vias placed at the output filtering capacitors. ac current loops formed by input filtering capacitors, output filtering capacitors, output inductors, and the regulator pins shall be minimized. gnd, agnd, dgnd pins shall be connected to the signal ground plane. compensation networks shall be placed close to the pins and referenced to the signal ground. v cc bypass capacitor shall be placed close to the pin. xr 77103 -a 0 r 5 rev1a
16/19 applications information (continued) typical applications cbst_ch1 rb_ch1 l out _ch1 rt_ch1 v in1 fb1 v out1 c out _ch1 c in _ch1 v in1 cbst_ch2 rb_ch2 l out _ch2 rt_ch2 v in2 fb2 v out2 c out _ch2 c in _ch2 v in2 xr77103-a0r5 vfb3 1 comp3 2 nc 3 vin 4 gnd 5 vcc 6 comp1 7 vfb1 8 bst1 9 vin1 10 lx1 11 lx1 12 lx2 13 lx2 14 vin2 15 bst2 16 pgood 24 23 22 21 20 dgnd 19 comp2 18 vfb2 17 bst3 32 vin3 31 lx3 30 lx3 29 vin 28 agnd 27 en 26 sync 25 e-pad 33 nc nc nc nc fb2 fb1 fb3 pg rpg v cc cp_ch2 rc_ch2 cc_ch2 cp_ch1 rc_ch1 cc_ch1 v cc v in c vcc cp_ch3 rc_ch3 cc_ch3 rb_ch3 l out _ch3 rt_ch3 fb3 v out3 c out _ch3 v in cbst_ch3 c in _ch3 v in3 v in3 c2_in v in rgnd sync en c1_in figure 32. typical applications schematic xr 77103 -a 0 r 5 rev1a
17/19 package description 1. all dimensioins are in millimeters 2. dimensions and tolerance per jedec mo-220 top view side view bottom view xr 77103 -a 0 r 5 rev1a
18/19 package description (continued) recommended land pattern xr 77103 -a 0 r 5 rev1a
www.exar.com 19/19 tel.: +1 (510) 668-7000 fax: +1 (510) 668-7001 email: powertechsupport@exar.com order information part number operating temperature range environmental rating package packaging quantity marking XR77103ELB-A0R5 -40c t j 125c rohs compliant, halogen free 32-pin, 4mm x 4mm tqfn package bulk exar xr77103 yywwf01 xxxxxxx xr77103elbtr-a0r5 3k/tape and reel xr77103evb-a0r5 xr77103-a0r5 evaluation board note: yy = year, ww = work week, xxxxxx = lot number. exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation conveys no license under any patent or other right and makes no representation that the circuits are free of patent infringement. while the information in this publication has been carefully checked, no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. exar, xr and the xr logo are registered trademarks of exar corporation. all other trademarks are the property of their respective owners. ?2016 exar corporation xr77103-a0r5_ds_030916 xr 77103 -a 0 r 5 rev1a 48760 kato road fremont, ca 94538 usa

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